Shared Cache Verification Engineer

Chiparama is seeking an experienced verification engineer to develop and execute test plans for shared L2 cache coherency in multi-core SoC designs. The role involves building UVM testbenches, creating portable stimulus scenarios for MOESI protocols, and debugging coherency bugs to achieve high coverage on intra/inter-cluster traffic. Responsibilities: Develop and execute test plans for shared L2 cache coherency in multi-core SoC designs; Building UVM testbenches; Creating portable stimulus scenarios for MOESI protocols; Integrating snoop controls and CCI interfaces; Running simulations/emulation; Debugging coherency bugs; Achieving high coverage on intra/inter-cluster traffic Qualifications: 10+ years in ASIC/SoC verification; Expertise in cache coherency (MOESI/MESI); Expertise in ARM/RISC-V architectures; Proficiency in SystemVerilog; Proficiency in UVM; Proficiency in assertions; Proficiency in formal methods; Proficiency in tools like Breker Trek or Synopsys VCS; Strong knowledge of AXI-ACE; Strong knowledge of ECC; Strong knowledge of low-power states; Strong knowledge of multi-threaded stress testing Required Skills: ASIC/SoC Verification, Cache Coherency, MOESI Protocol, MESI Protocol, ARM Architecture, RISC-V Architecture, SystemVerilog, UVM, Assertions, Formal Methods, Breker Trek, Synopsys VCS, AXI-ACE, ECC, Low-Power States, Multi-Threaded Stress Testing, Many-Core Designs, Silicon Validation